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CAT93C56, CAT93C57
2-Kb Microwire Serial CMOS EEPROM
FEATURES
High speed operation: 2MHz 1.8V to 5.5V supply voltage range Selectable x8 or x16 memory organization Sequential read Software write protection Power-up inadvertant write protection Low power CMOS technology 1,000,000 Program/erase cycles 100 year data retention Industrial temperature ranges RoHS-compliant 8-pin PDIP, SOIC, TSSOP and 8-pad TDFN packages For Ordering Information details, see page 16.
DESCRIPTION
The CAT93C56/57 is a 2-Kb CMOS Serial EEPROM device which is organized as either 128 registers of 16 bits (ORG pin at VCC) or 256 registers of 8 bits (ORG pin at GND). Each register can be written (or read) serially by using the DI (or DO) pin. The CAT93C56/57 features sequential read and self-timed internal write with autoclear. On-chip Power-On Reset circuitry protects the internal logic against powering up in the wrong state.
PIN CONFIGURATION
PDIP (L) SOIC (V, X) TSSOP (Y) TDFN (VP2, ZD4*) CS SK DI DO 1 2 3 4 8 VCC 7 NC 6 ORG 5 GND NC VCC CS SK
FUNCTIONAL SYMBOL
VCC
SOIC (W*) 1 2 3 4 8 ORG 7 GND 6 DO 5 DI
ORG CS SK DI CAT93C56 CAT93C57 DO
* TDFN 3x3mm (ZD4) and SOIC (W) rotated pin-out packages are available for CAT93C57 and CAT93C56, Rev. E only (not recommended for new designs of CAT93C56)
GND
PIN FUNCTION
Pin Name CS SK DI DO VCC GND ORG NC Function Chip Select Clock Input Serial Data Input Serial Data Output Power Supply Ground Memory Organization No Connection
Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 pin is selected. If the ORG pin is left unconnected, then am internal pullup device will select the x16 organization
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Doc. No. MD-1088 Rev. P
CAT93C56, CAT93C57
Absolute Maximum Ratings(1) Parameters Storage Temperature Voltage on Any Pin with Respect to Ground Reliability Characteristics(3) Symbol NEND(4) TDR Parameter Endurance Data Retention Min 1,000,000 100 Units Program/ Erase Cycles Years
(2)
Ratings -65 to +150 -0.5 to +6.5
Units C V
D.C. OPERATING CHARACTERISTICS, CAT93C56, Die Rev. G - New Product VCC = +1.8V to +5.5V, TA=-40C to +85C unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2
Notes: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20 ns. (3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Block Mode, VCC = 5V, 25C
Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16 Mode) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage
Test Conditions fSK = 1MHz, VCC = 5.0V fSK = 1MHz, VCC = 5.0V VIN = GND or VCC, CS = GND ORG = GND VIN = GND or VCC, CS = GND ORG = Float or VCC VIN = GND to VCC VOUT = GND to VCC, CS = GND 4.5V VCC < 5.5V 4.5V VCC < 5.5V 1.8V VCC < 4.5V 1.8V VCC < 4.5V 4.5V VCC < 5.5V, IOL = 2.1mA 4.5V VCC < 5.5V, IOH = -400A 1.8V VCC < 4.5V, IOL = 1mA 1.8V VCC < 4.5V, IOH = -100A
Min
Max 1 500 2 1 1 1
Units mA A A A A A V V V V V V V V
-0.1 2 0 VCC x 0.7 2.4
0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 0.2
VCC - 0.2
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CAT93C56, CAT93C57
D.C. OPERATING CHARACTERISTICS, CAT93C56/57, Die Rev. E - Mature Product (CAT93C56, Rev. E - NOT RECOMMENDED FOR NEW DESIGNS) VCC = +1.8V to +5.5V, TA=-40C to +125C unless otherwise specified. Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VIL2 VIH2 VOL1 VOH1 VOL2 VOH2 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16 Mode) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Test Conditions fSK = 1MHz, VCC = 5.0V fSK = 1MHz, VCC = 5.0V VIN = GND or VCC, CS = GND ORG = GND VIN = GND or VCC, CS = GND ORG = Float or VCC VIN = GND to VCC VOUT = GND to VCC, CS = GND 4.5V VCC < 5.5V 4.5V VCC < 5.5V 1.8V VCC < 4.5V 1.8V VCC < 4.5V 4.5V VCC < 5.5V, IOL = 2.1mA 4.5V VCC < 5.5V, IOH = -400A 1.8V VCC < 4.5V, IOL = 1mA 1.8V VCC < 4.5V, IOH = -100A VCC - 0.2 2.4 0.2 -0.1 2 0 VCC x 0.7 Min Max 3 500 10 10 1 1 0.8 VCC + 1 VCC x 0.2 VCC + 1 0.4 Units mA A A A A A V V V V V V V V
PIN CAPACITANCE TA = 25C, f = 1MHz, VCC = 5V Symbol COUT CIN
Notes: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods.
(1) (1)
Test Output Capacitance (DO) Input Capacitance (CS, SK, DI, ORG)
Conditions VOUT = 0V VIN = 0V
Min
Typ
Max 5 5
Units pF pF
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CAT93C56, CAT93C57
A.C. CHARACTERISTICS(1), CAT93C56, Die Rev. G - New Product VCC = +1.8V to +5.5V, TA = -40C to +85C, unless otherwise specified. Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(2) tEW tCSMIN tSKHI tSKLOW tSV SKMAX Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 0.25 0.25 0.25 0.25 2000 Min 50 0 100 100 0.25 0.25 100 5 Max Units ns ns ns ns s s ns ms s s s s kHz
A.C. CHARACTERISTICS (1), CAT93C56/57, Die Rev. E - Mature Product (CAT93C56 Rev. E - NOT RECOMMENDED FOR NEW DESIGNS) Limits Symbol tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(2) tEW tCSMIN tSKHI tSKLOW tSV SKMAX
Notes: (1) (2) Test conditions according to "A.C. Test Conditions" table. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods.
Parameter CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency
VCC = 1.8V - 5.5V Min 200 0 400 400 1 1 400 10 1 1 1 1 DC 250 Max
VCC = 2.5V - 5.5V Min 100 0 200 200 0.5 0.5 200 10 0.5 0.5 0.5 0.5 DC 500 Max
VCC = 4.5V - 5.5V Min 50 0 100 100 0.25 0.25 100 10 0.25 0.25 0.25 0.25 DC 1000 Max
Units ns ns ns ns s s ns ms s s s s kHz
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CAT93C56, CAT93C57
POWER-UP TIMING(1) (2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max 1 1 Units ms ms
Notes: (1) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
A.C. Test Conditions Input Rise and Fall Times Input Pulse Voltages Timing Reference Voltages Input Pulse Voltages Timing Reference Voltages Output Load
50 ns
0.4V to 2.4V 0.8V, 2.0V 0.2VCC to 0.7VCC 0.5VCC 4.5V VCC 5.5V 4.5V VCC 5.5V 1.8V VCC 4.5V 1.8V VCC 4.5V
Current Source IOLmax/IOHmax; CL=100pF
DEVICE OPERATION
The CAT93C56/57 is a 2048-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C56/57 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 10-bit instructions for 93C57 or seven 11bit instructions for 93C56 control the reading, writing and erase operations of the device. When organized as X8, seven 11-bit instructions for 93C57 or seven 12-bit instructions for 93C56 control the reading, writing and erase operations of the device. The CAT93C56/57 operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state Figure 1. Sychronous Data Timing
tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH
except when reading data from the device, or when checking the ready/busy status after a write operation. The serial communication protocol follows the timing shown in Figure 1. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin.
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CAT93C56, CAT93C57
The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 7-bit address (CAT93C57) / 8-bit address (CAT93C56) (an additional bit when organized X8) and for write INSTRUCTION SET Instruction READ ERASE WRITE EWEN EWDS ERAL WRAL Device Type 93C56
(1)
operations a 16-bit data field (8-bit for X8 organi- zations). The instruction format is shown in Instruction Set table.
Start Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Opcode 10 10 11 11 01 01 00 00 00 00 00 00 00 00 x8 A8-A0 A7-A0 A8-A0 A7-A0 A8-A0 A7-A0 11XXXXXXX 11XXXXXX 00XXXXXXX 00XXXXXX 10XXXXXXX 10XXXXXX 01XXXXXXX 01XXXXXX x16 A7-A0 A6-A0 A7-A0 A6-A0 A7-A0 A6-A0 11XXXXXX 11XXXXX 00XXXXXX 00XXXXX 10XXXXXX 10XXXXX 01XXXXXX 01XXXXX x8
Data x16 Comments Read Address AN-A0 Clear Address AN-A0 D7-D0 D7-D0 D15-D0 D15-D0 Write Address AN-A0 Write Enable Write Disable Clear All Addresses D7-D0 D7-D0 D15-D0 D15-D0 Write All Addresses
93C57 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57 93C56(1) 93C57
Note: (1) Address bit A8 for 256x8 organization and A7 for 128x16 organization are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands.
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(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT93C56, CAT93C57
Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93C56/57 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the CAT93C56/57, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the Figure 2. READ Instruction Timing
SK
address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. The READ instruction timing is illustrated in Figure 2. Erase/Write Enable and Disable The CAT93C56/57 powers up in the write disable state. Any writing after power-up or after an EWDS (erase/write disable) instruction must first be preceded by the EWEN (erase/write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93C56/57 write and erase instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/disable status. The EWEN and EWDS instructions timing is shown in Figure 3.
CS Don't Care AN DI 1 1 0 tPD0 DO HIGH-Z AN-1 A0
Dummy 0
D15 . . . D0 or D7 . . . D0
Address + 1 D15 . . . D0 or D7 . . . D0
Address + 2 D15 . . . D0 or D7 . . . D0
Address + n D15 . . . or D7 . . .
Figure 3. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
* * ENABLE = 11 DISABLE = 00
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Doc. No. MD-1088 Rev. P
CAT93C56, CAT93C57
Write After receiving a WRITE command (Figure 4), address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Figure 4. Write Instruction Timing
SK tCSMIN CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY tHZ HIGH-Z AN-1 A0 DN D0 STATUS VERIFY STANDBY
Erase Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN (Figure 5). The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SaK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state.
Figure 5. Erase Instruction Timing
SK
CS AN DI 1 1 1 tSV AN-1 A0
STATUS VERIFY tCS
STANDBY
DO
HIGH-Z
tHZ BUSY tEW READY HIGH-Z
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CAT93C56, CAT93C57
Erase All Upon receiving an ERAL command (Figure 6), the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical "1" state. Figure 6. ERAL Instruction Timing
SK
Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN (Figure 7). The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93C56/57 can be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.
CS
STATUS VERIFY tCS
STANDBY
DI
1
0
0
1
0 tSV tHZ BUSY tEW READY HIGH-Z
DO
HIGH-Z
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY tCSMIN
STANDBY
DI
1
0
0
0
1
DN
D0 tSV tHZ BUSY tEW READY HIGH-Z
DO
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Doc. No. MD-1088 Rev. P
CAT93C56, CAT93C57
PACKAGE OUTLINE DRAWINGS
PDIP 8-Lead 300mils (L)
SYMBOL
MIN
NOM
MAX
A A1 A2 b
E1
5.33 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 7.87 2.92 3.30 3.30 0.46 1.52 0.25 9.27 7.87 2.54 BSC 6.35 7.11 10.92 3.80 4.95 0.56 1.78 0.36 10.16 8.25
b2 c D E e E1 eB
PIN # 1 IDENTIFICATION D
L
TOP VIEW
E
A
A2
A1 b2 L c
e SIDE VIEW
b
eB
END VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC MS-001.
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(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT93C56, CAT93C57
SOIC 8-Lead 150mils (V, W)
SYMBOL
MIN
NOM
MAX
A A1 b c
E1 E
1.35 0.10 0.33 0.19 4.80 5.80 3.80 1.27 BSC 0.25 0.40 0
1.75 0.25 0.51 0.25 5.00 6.20 4.00 0.50 1.27 8
D E E1 e h L
PIN # 1 IDENTIFICATION TOP VIEW
D
h
A1
A
c
e
b
L END VIEW
SIDE VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Angles in degrees. Complies with JEDEC MS-012.
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Doc. No. MD-1088 Rev. P
CAT93C56, CAT93C57
SOIC 8-Lead EIAJ (208mils) (X)
SYMBOL
MIN
NOM
MAX
A A1 b c
E1 E
2.03 0.05 0.36 0.19 5.13 7.75 5.13 1.27 BSC 0.51 0 0.76 8 0.25 0.48 0.25 5.33 8.26 5.38
D E E1 e L
PIN#1 IDENTIFICATION TOP VIEW
D
A
e
b
A1
L
c END VIEW
SIDE VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Angles in degrees. Complies with EIAJ EDR-7320. 12
Doc. No. MD-1088 Rev. P
(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT93C56, CAT93C57
TSSOP 8-Lead 4.4mm (Y)
b
SYMBOL
MIN
NOM
MAX
A A1 A2 b c
E1 E
1.20 0.05 0.80 0.19 0.09 2.90 6.30 4.30 3.00 6.40 4.40 0.65 BSC 1.00 REF 0.50 0 0.60 0.75 8 0.90 0.15 1.05 0.30 0.20 3.10 6.50 4.50
D E E1 e L L1 1
e
TOP VIEW
D c
A2
A
1
A1 SIDE VIEW
L1 END VIEW
L
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Angles in degrees. Complies with JEDEC MO-153.
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Doc. No. MD-1088 Rev. P
CAT93C56, CAT93C57
TDFN 8-Pad 2 x 3mm (VP2)
D
A
e
b
E
E2 PIN#1 IDENTIFICATION
A1 PIN#1 INDEX AREA D2 L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBO L A A1 A2 A3 b D D2 E E2 e L
MIN 0.70 0.00 0.45 0.20 1.90 1.30 2.90 1.20 0.20
NOM 0.75 0.02 0.55 0.20 REF 0.25 2.00 1.40 3.00 1.30 050 TYP 0.30
MAX 0.80 0.05 0.65 0.30 2.10 1.50 3.10 1.40 0.40
A2 A3
FRONT VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC MO-229.
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(c) Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT93C56, CAT93C57
TDFN 8-Pad 3 x 3mm (ZD4)
D A
e
b L
E
E2
PIN#1 ID
PIN#1 INDEX AREA
A1
D2
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
NOM
MAX
A A1 A3 b D D2 E E2 e L
0.70 0.00 0.23 2.90 2.20 2.90 1.40 0.20
0.75 0.02 0.20 REF 0.30 3.00 2.30 3.00 1.50 0.65 TYP 0.30
0.80 0.05
A A3 A1
0.37 3.10 2.40 3.10 1.60 0.40
FRONT VIEW
For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf.
Notes: (1) (2) All dimensions are in millimeters. Complies with JEDEC MO-229.
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CAT93C56, CAT93C57
EXAMPLE OF ORDERING INFORMATION
CAT93C56, Die Rev. G, New Product
Prefix CAT
Company ID
Device # Suffix 93C56 V
Package PDIP SOIC, JEDEC SOIC, EIAJ(4) TSSOP TDFN (2x3mm)
I
Temperature Range I = Industrial (-40C to 85C)
-G
Lead Finish Blank: Matte-Tin G: NiPdAu
T3
Product Number 93C56
L: V: X: Y: VP2:
Tape & Reel T: Tape & Reel 2: 2000 units/Reel(4) 3: 3000 units/Reel
Notes: (1) (2) (3) (4) (5) All packages are RoHS-compliant (Lead-free, Halogen-free). The standard lead finish is NiPdAu. The device used in the above example is a CAT93C56VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C56XI-T2. For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
CAT93C56/57, Die Rev. E, Mature Product (CAT93C56, Rev. E - Not Recommended for new Designs)
Prefix CAT
Company ID
Device # Suffix 93C56 V I
Temperature Range I = Industrial (-40C to 85C) A = Automotive (-40C to 105C) E = Extended (-40C to 125C) Package PDIP SOIC, JEDEC SOIC, JEDEC SOIC, EIAJ(5) TSSOP TDFN (3x3mm) Operating Voltage Blank: VCC = 2.5V to 5.5V 1.8: VCC = 1.8V to 5.5V
-1.8
-G T3
Rev E(4)
Die Revision 93C56: E 93C57: E
Product Number 93C56 93C57 L: V: W: X: Y: ZD4:
Notes: (1) (2) (3) (4) (5) (6)
Tape & Reel T: Tape & Reel (5) 2: 2000 units/Reel 3: 3000 units/Reel
Lead Finish Blank: Matte-Tin G: NiPdAu
All packages are RoHS-compliant (Lead-free, Halogen-free). The standard finish is NiPdAu. The device used in the above example is a CAT93C56VI-1.8-GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, NiPdAu finish, Tape & Reel.) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE). For additional information, please contact your Catalyst sales office. For SOIC, EIAJ (X) package the standard lead finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT93C56XI-T2. For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
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CAT93C56, CAT93C57
REVISION HISTORY
Date 05/14/04 Rev. L Comments New Data Sheet Created From CAT93C46/56/57/66/86. Parts CAT93C56, CAT93C56, CAT93C57, CAT93C56/57, CAT93C76 and CAT93C86 have been separated into single data sheets Updated Instruction Set Updated Description Update Features Update Pin Configuration Update Functional Symbol Update Pin Functions Update D.C. Operating Characteristics (VCC Range) Update A.C. Characteristics (VCC Range) Update Ordering Information Updated Features/Description Remove "Die Rev E" from the title Update Pin Configuration / Packages Update Absolute Maximum Rating Update Reliability Characteristics Update D.C. Operating Characteristics Added D.C. / A.C. Characteristics for CAT93C56 Die Rev G Rearrange / Format Text and Figures Update Package Outline Drawings Added Example of Ordering Information for CAT93C56 Die Rev. G Add MD- to document number
10/13/06 03/18/05 10/13/06
M N O
08/21/07
P
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Doc. No. MD-1088 Rev. P
Copyrights, Trademarks and Patents (c) Catalyst Semiconductor, Inc. Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: Beyond MemoryTM, DPPTM, EZDimTM, LDDTM, MiniPotTM and Quad-ModeTM Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES. Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc. Corporate Headquarters 2975 Stender Way Santa Clara, CA 95054 Phone: 408.542.1000 Fax: 408.542.1200 www.catsemi.com
Document No: MD-1088 Revision: P Issue date: 08/21/07

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